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innovasic semiconductor ? copyright ? 2005 ia88c00 microcontroller data sheet
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 2 of 80 1.888.824.4184 data sheet contents please note........................................ ................................................... ................................................... .......4 features ........................................... ................................................... ................................................... .........4 general description ................................ ................................................... ................................................... .4 architecture....................................... ................................................... ................................................... .....13 pin descriptions ................................... ................................................... ................................................... ..13 registers.......................................... ................................................... ................................................... .......14 working register window ............................ ................................................... .......................................15 register list ...................................... ................................................... ................................................... .17 mode and control registers ......................... ................................................... ............................................20 instruction summary................................ ................................................... .................................................45 opcode map ......................................... ................................................... ................................................... ..52 instructions....................................... ................................................... ................................................... ......53 interrupts ......................................... ................................................... ................................................... .......56 interrupt programming model ........................ ................................................... ......................................58 functional overview................................ ................................................... .............................................58 stack operation.................................... ................................................... ................................................... ..58 counter/timers ..................................... ................................................... ................................................... .59 wdt................................................ ................................................... ................................................... .......59 stop mode .......................................... ................................................... ................................................... ....59 halt mode .......................................... ................................................... ................................................... ....60 i/o ports .......................................... ................................................... ................................................... .......61 port 0 ............................................. ................................................... ................................................... .....61 port 1 ............................................. ................................................... ................................................... .....61 port 2 and 3 ....................................... ................................................... ................................................... .62 port 4 ............................................. ................................................... ................................................... .....62 uart............................................... ................................................... ................................................... ......62 pins............................................... ................................................... ................................................... ......63 transmitter ........................................ ................................................... ................................................... .63 receiver........................................... ................................................... ................................................... ...63 address space ...................................... ................................................... .................................................64 cpu program memory ................................. ................................................... ........................................64 cpu data memory.................................... ................................................... ............................................64 absolute maximum ratings ........................... ................................................... ..........................................66 standard test conditions ........................... ................................................... ...............................................66 figure 63. standard test load ................................................... ................................................... .......................66 dc characteristics ................................. ................................................... ................................................... 67 input handshake.................................... ................................................... ................................................73 output handshake................................... ................................................... ..............................................74 eprom read cycle ................................... ................................................... ..........................................75
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 3 of 80 1.888.824.4184 wait timing ........................................ ................................................... ................................................... ...75 de-multiplexed bus timing ......................... ................................................... ...........................................76 package information ................................ ................................................... .................................................77 ordering information ............................... ................................................... .................................................80
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 4 of 80 1.888.824.4184 please note included under ordering information on page 68 are enhanced rohs-compliant versions of the ia88c00. however, standard packaged or non rohs-compliant ve rsions of the ia88c00 microcontroller are still available. features ? fully form, fit and function compatible with the s uper8 (z88c00) ? available in 48-, and 68-pin packages ? fully compatible with the super8 instruction set ? rich program register set ? 128 kbytes external program address space ? built-in direct memory access (dma) ? two programmable 16-bit counter/timers with 8-bit p rescalers ? up to 32 general purpose i/o lines including specia l handshake funtionality ? robust interrupt structure ? watch-dog timer general description the ia88coo is a form, fit and function replacement for the original zilog ? z88c00 microcontroller. innovasic semiconductor produces replacement ics us ing its miles tm , or managed ic lifetime extension system, cloning technology. this technolo gy produces replacement ics far more complex than "emulation" while ensuring they are compatible with the original ic. miles tm captures the design of a clone so it can be produced even as silicon technol ogy advances. miles tm also verifies the clone against the original ic so that even the "undocumented feat ures" are duplicated. this data sheet documents all necessary engineering information about the ia88coo including functional and i/o descriptions, electrical charact eristics, and applicable timing. the function block diagram of the ia88c00 is shown in figure 1. the device is available in a 48-pin di p (figure 2) and a 68-pin plcc package (figure 3). th e pin functions of the ia88coo are outlined in figure 6. pin functions .
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 5 of 80 1.888.824.4184 uart port 0 port 2 port 3 interrupt control counters/ timers (2) port 4 port 1 machine timing watchdog timer dma system registers (pc) (instruction pointer) alu instruction decode register file control registers cpu i/o (bit programmable) or control (irq, timer, uart) address or i/o (bit programmable) address or i/o (byte programmable) 8 xtal1 xtal2 r//w /ds /as /reset i/o (bit programmable) demux figure 1. functional block diagram
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 6 of 80 1.888.824.4184 ia88c00 dip p00 p01 p07 p34 /as gnd p42 /reset p36 p27 p26 p30 p06 p40 p04 /ds p43 r/w p37 p05 p11 p02 p03 p35 p41 p12 p13 p14 p15 p16 p17 p24 p25 +5v xtal2 xtal1 p44 p45 p46 p47 p22 p32 p33 p23 p20 p21 p31 p10 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 figure 2. 48-lead dip package
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 7 of 80 1.888.824.4184 figure 3. 48-lead dip pin assignments pin # symbol function direction 1-8 p10-17 port 1, pins 0,1,3,4,5,6,7 in/output 9-10 p24-25 port 2, pins 4,5 in/output 11 vcc power supply input 12 xtal2 crystal oscillator output 13 xtal1 crystal oscillator output 14-17 p44-47 port 4, pins 4,5,6,7 input/output 18 p22 port 2, pin 2 input/output 19-20 p32-21 port 2, pins 2,3 input/output 21-23 p23-21 port 2, pins 3,0,1 input/output 24-25 p31-30 port 3, pins 1,0 input/output 26-27 p26-27 port 2, pins 6,7 input/output 28-29 p37-36 port 3, pins 7,6 in/output 30 /reset reset input 31 r/w read/write output 32-33 p43-42 port 4, pins 3,2 in/output 34 gnd ground input 35-36 p41-40 port 4, pins 1,0 in/output 37 /ds data strobe output 38 /as address strobe output 39-40 p35-34 port 3, pins 5,4 in/output 41-48 p07-00 port 0, pins 7,6,5,4,3,2,1,0 in/output
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 8 of 80 1.888.824.4184 figure 4. 68-lead plcc package p43 r/w nc nc nc vcc p06 p07 p34 p35 /as /ds p40 p41 gnd gnd p42 nc nc reset p36 p37 p27 p26 p30 nc p31 p21 p20 p23 p33 p32 nc p22 nc nc p47 p46 p45 p44 vtal1 xtal2 vcc gnd vcc p25 p24 p17 p16 de-mux vcc nc nc p05 p04 p03 p02 p01 p00 gnd nc p10 p11 p12 p13 p14 p15 nc ia88c00 (top view) 10 11 1 2 13 1 4 1 5 16 17 18 19 2 0 21 22 2 3 2 4 25 2 6 60 59 5 8 57 5 6 5 5 54 53 52 51 5 0 49 48 4 7 4 6 45 4 4 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 9 of 80 1.888.824.4184 figure 5. 68-lead plcc-pin assignments pin # symbol function direction 1 nc note connected 2-7 p10-15 port 1, pins 0,1,2,3,4,5 in/output 8-10 nc not connected 11 vcc power supply input 12 de-mux de-multiplex pin input 13-14 p16-17 port 1, pins 6,7 in/output 15-16 p24-25 port 2, pins 4,5 in/output 17 vcc power supply input 18 gnd ground input 19 vcc power supply input 20 xtal2 crystal oscillator in/output 21 xtal1 crystal oscillator in/output 22-25 p44-47 port 4, points 4,5,6,7 in/output 26-27 nc not connected 28 p22 port 2, pin 2 in/output 29 nc not connected 30-31 p32-33 port 3, pins 2,3 in/output 32-34 p23-21 port 2, pins 3,0,1 in/output 35 p31 port 3, pin 1 in/output 36 nc not connected 37 p30 port 3, pin 0 in/output 38-39 p26-27 port 2, pins 6,7 in/output 40-41 p37-36 port 3, pins 7,6 in/output 42 /reset reset input 43-44 nc not connected 45 r//w read/write output 46-47 p43-42 port 4, pins 3,2 in/output 48-49 gnd ground input 50-51 p41-40 port 4, pins 1,0 in/output 52 /ds data strobe output 53 /as address strobe output 54-55 p43-42 port 3, pins 5,4,3,2 in/output 56-57 p07-06 port 0, pins 7,6 in/output 58 vcc power supply input 59-61 nc not connected 62-65 p05-02 port 0, pins 5,4,3,2 in/output 66 gnd ground input
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 10 of 80 1.888.824.4184 67 nc not connected input/output 68 gnd ground input
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 11 of 80 1.888.824.4184 p07 p14 p15 p16 p17 p14 41 56 7 8 36 30 /reset +5v 11 xtal1 13 gnd 34 xtal2 12 p47 17 p46 16 p45 14 p44 28 p37 29 p36 39 p35 40 p34 20 p32 24 p31 25 p30 27 p27 26 p26 10 p25 9 p24 21 p23 18 p22 23 p20 22 31 r//w /ds 37 /as 38 p00 48 p01 47 p02 46 p03 45 p04 44 p05 43 p06 42 p21 22 p10 1 p11 2 p12 3 p33 19 p13 4 p15 35 p16 33 p17 32 timing and control port 0 port 1 port 4 (1/2) power clock port 2 port 3 port 4 (1/2) ia88c00
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 12 of 80 1.888.824.4184 figure 6. pin functions
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 13 of 80 1.888.824.4184 architecture ia88c00 maintains program model compatibility with the super8 architecture, including 268 general purpose registers and 57 registers for control and mode functions. the instruction set, is also fully binary compatibl e supporting all instructions, including multiply a nd divide instructions and provisions for bcd operatio ns. the peripheral set maintains register/ program mode l compatibility. robust serial communications are provided by an on-board uart. counter/timers are p rovided for time-sensitive/control loop applications. a watchdog timer is provided for proc essor sanity. pin descriptions /as address strobe ( output, active low ) the rising edge of this output indicates that addre ss, r/w, and dm (when appropriate) are valid. /ds data strobe ( output, active low the leading edge of this signal indicates that data is valid during a write cycle. the trailing edge of this signal is used to latch d ata into the ia88c00 during a read cycle. p00-p07, p10-p17, p20-p27, p30-p37, p40-p47, port i/o lines ( input/output ) input/output ports configured under program control . specific functions include: port 1 serves as the multiplexed address/data port. it se rves as the data bus de-multiplexed mode, and port 0 pins can be used as additional address lines or general purpose i/o. ports 2 and 3 provide support for interrupts, the uart and the t imers. alternatively, they can be programmed as general pu rpose i/o. port 4 is used for general i/o or as the lower address by te in de-mux mode. /reset ( input, active low ) reset input. reset vector is address 0020h. r/w read/write ( output ) when high, the current bus operation is a read. whe n low, the current bus operation is a write.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 14 of 80 1.888.824.4184 xtal1, xtal2 ( crystal oscillator input ) crystal inputs for the internal oscillator. all port pins are configured as inputs (high impeda nce) during reset, except for port 1 and port 0. po rt 1 is configured as a multiplexed address/ data bus. port 0 pins p00-p04 are configured as address out. and pins p05-p07 are configured as inputs. registers the ia88c00 supports a 256-byte register address sp ace. addresses 00h-bfh contain two sets of registers. set one contains control registers that are only accessible by register direct commands. se t two contains data registers that are only available via register indirect, indexed, stack and dma commands , note that address space e0h to ffh in set one is fu rther divided into two banks. the state of bank se lect bit in the flag register determines which bank is a ccessed. the register space is shown in figure 7.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 15 of 80 1.888.824.4184 set one ffh eoh dfh doh cfh coh mode and control registers (register addressing only) system register: stack, flags, ports, etc. (register addressing only) working register (working register addressing only) bank 1 bank 0 data registers (indirect register, indexed, stack or dma access only) set two ffh coh cfh ooh data registers (all addressing modes) 192 bytes 256 bytes figure 7. ia88c00registers working register window working registers are those registers found within a moveable 8-register section of the register space . these moveable 8-register sections are defined by r egister pointers rp0 and rp1, which are control registers r214 and r215. short 4-bit addresses are used to access working re gisters. the process of accessing working registers , shown in a section of figure 7, occurs as follows:
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 16 of 80 1.888.824.4184 1. high order bit of the 4-bit address selects one of the two register pointers (0 selects rp0; 1 sele cts rp1). 2. live high order bits in the register pointer sel ect an 8-register (contiguous) slice of the registe r space. 3. three low order bits of the 4-bit address select one of the eight registers in the slice. the process results in linking together the five bi ts from the register pointer to the three bits from the address to form an 8-bit address. the three bits f rom the address will always point to an address wit hin the same eight registers, as long as the address in the register pointer remains unchanged. changing the five high bits in control registers r2 14 for rp9 and r215 for rp1 allows the register pointers to be moved. using full 8-bit addressing allows the working regi sters to be accessed. the lower nibble is used simi larly to the 4-bit addressing described above when an 8-b it logical address in the range 192 to 207 (c0 to c f) is specified. this is shown in section b. of figure 8. together they create 8-bit register address selects rp0 or rp1 rp0 (r214) rp1 (r215) address opcode register pointer provides five high-order bits 4-bit address provides three low-order bits a. 4-bit addressing selects rp0 or rp1 rp0 (r214) rp1 (r215) address register pointer provides five high-order bits b. 8-bit addressing 8-bit physical address 1 1 0 0 8-bit logical address three low- order bits figure 8. working register window physical registers 192 to 207 can be accessed only when selected by a register pointer. this is becaus e any direct access to logical addresses 192 to 207 i nvolves the register pointers. after a reset, rp0 p oints to r192 and rp1 points to r200.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 17 of 80 1.888.824.4184 register list figure 9 displays the ia88c00registers. for more de tails, see the registers presented under mode and control registers. figure 9. ia88c00registers decimal address hexadecimal mnemonic function general purpose registers 00-192 00-bf - general purpose (all address modes) 192-207 00-cf - working register (direct only) 192-255 c0-ff - general purpose (indirect only) mode and control registers 208 d0 p0 port 0 i/o bits 209 d1 p1 port 1 (i/o only) 210 d2 p2 port 2 211 d3 p3 port 3 212 d4 p4 port 4 213 d5 flags system flags register 214 d6 rp0 register pointer 0 215 d7 rp1 register pointer 1 216 d8 sph stack pointer low byte 217 d9 spl stack pointer high byte 218 da iph instruction pointer high byte 219 db ipl instruction pointer low byte 220 dc irq interrupt request 221 dd imr interrupt mask register 222 de sym system mode register 223 df hmr hall mode register 224 e0 bank 0 coct ctr 0 control bank 1 com ctr 0 mode 225 e1 bank 0 c1ct ctr 1 control bank 1 c1m ctr 1 mode 226 e2 bank 0 coch ctr 0 capture register, bits 8- 15 bank 1 cotch ctr 0 timer constant, bits 8-15 227 e3 bank 0 cocl ctr 0 capture register, bits 0- 7 bank 1 cotcl ctr 0 time constant, bits 0-7 228 e4 bank 0 c1ch ctr 1 capture register, bits 8- 15 bank 1 c1tch ctr 1 time constant, bits 8-15 229 e5 bank 0 c1cl ctr 1 capture register, bits 0- 7 bank 1 c1tcl ctr 1 time constant, bits 0-7 230 e6 bank 0 ctprs counter prescaler 230 e6 bank 1 wdtsmr watch-dog/stop mode register 235 eb bank 0 utc uart transmit control
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 18 of 80 1.888.824.4184 236 ec bank 0 urc uart receive control 237 ed bank 0 uie uart interrupt enable 238 ee bank 0 uti transmit interrupt register 239 ef bank 0 uio uart data 240 f0 bank 0 pom port 0 mode bank 1 dch dma count, bits 8-15 241 f1 bank 0 pm port mode register bank 0 dcl dma count, bits 0-7 244 f4 bank 0 h0c handshake channel 0 control 245 f5 bank 0 h1c handshake channel 1 control 246 f6 bank 0 p4d port 4 direction 247 f7 bank 0 p4od port 4 open drain 248 f8 bank 0 p2am port 2/3 a mode bank 1 ubgh uart baud rate generator, bits 8-15 249 f9 bank 0 p2bm port 2/3 b mode bank 1 ubgl uart baud rate generator, bits 0-7 250 fa bank 0 p2cm port 2/3 c mode bank 1 uma uart mode a 251 fb bank 0 p2dm port 2/3 d mode bank 1 umb uart mode b 252 fc bank 0 p2aip port 2/3 a interrupt pending 253 fd bank 0 p2bip port 2/3 b interrupt pending 254 fe bank 0 emt external memory timing bank 1 wumch wake-up match register 255 ff bank 0 ipr interrupt priority register bank 0 wumsk wake-up mask register
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 19 of 80 1.888.824.4184
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 20 of 80 1.888.824.4184 mode and control registers figure 10. r213 (d5) flags system flags register bit 7 6 5 4 3 2 1 0 carry zero sign overflow decimal adjust half- carry fast interrupt bank initial value ? ? ? ? ? ? ? ? read/write r r r r r r r r/w the flag register contains eight bits that describe the current status of the processor. four of these bits can be tested and used with conditional jump instructio ns. two others are used for bcd arithmetic. also contained in the flag register are the bank address bit and the fast interrupt status bit. bit 7: carry flag - this is set to 1 if the result from an arithmeti c operation generates carry out of, or borrow into, bit 7. bit 6: zero flag - for arithmetic and logical operations, this flag is set to 1 if the result of the operation is 0. for operations that test bits in a register, the 0 bit is set to 1 if the result is 0. for rotate a nd shift operations, this bit is set to 1 if the result is 0 . bit 5: sign flag - following arithmetic, logical, rotate or shift o perations, this bit identifies the state of the msb of the result. a 0 indicates a positive num ber and a 1 indicates a negative number. bit 4: overflow flag - this flag is set to 1 when the result of a two's -complement operation was greater than 127 or less than -128. it is also cleared to 0 during logical operations. bit 3: decimal adjust - this bit is used to specify what type of instruc tion was executed last during bcd operations, so a subsequent decimal adjust operatio n can function correctly. this bit is not usually accessible to programmers and cannot be used as a t est condition. bit 2: half-carry flag - this bit is set to 1 whenever an addition genera tes a carry out of bit 3, or when a subtraction borrows out of bit 4. this bit is used by the decimal adjust (da) instruction to convert t he binary result of a previous addition or subtraction into the correct decimal (bcd) result. this flag a nd the decimal adjust flag are not usually accessed by use rs. bit 1: fast interrupt status - this bit is set during a fast interrupt cycle an d reset during the iret following interrupt servicing. when set, this bit i nhibits all interrupts and causes the fast interrup t return to be executed when the iret instruction is fetched . bit 0: bank address - this bit is used to select one of the register b anks (0 or 1) between (decimal) addresses 224 and 255. it is cleared by the sb0 ins truction and set by the sb1 instruction.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 21 of 80 1.888.824.4184 figure 11. r214 (d6) rp0 register pointer 0 bit 7 6 5 4 3 2 1 0 rp7 rp6 rp5 rp4 rp3 not used not used not used initial value 1 1 0 0 0 - - - read/write r/w r/w r/w r/w r/w - - - register pointer 0 (rp0) defines a moveable, 8-regi ster section of the register space. the registers w ithin these spaces are called working registers. rp0 is u sed in addressing modes where the register operand is expressed as a 4-bit address. at reset, rp0 points to r192. figure 12. r215 (o7) rp1 register pointer 1 bit 7 6 5 4 3 2 1 0 rp7 rp6 rp5 rp4 rp3 not used not used not used initial value ? ? ? ? ? ? ? ? read/write r/w r/w r/w r/w r/w r/w r/w r/w register pointer 1 (rp1) defines a moveable, 8-regi ster section of the register space. the registers w ithin these spaces are called working registers. rp1 is u sed in addressing modes where the register operand is expressed as a 4-bit address. at reset, rp0 points to r200. figure 13. r216 (d8) sph stack pointer bit 7 6 5 4 3 2 1 0 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w stack operations are supported in the register file or in data memory. bit 1 in the external memory ti ming register (r254b0) selects between the two. register pair r216-r217 forms the stack pointer use d for all stack operations. r216 is the msb and r217 is the lsb.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 22 of 80 1.888.824.4184 the stack pointer always points to data stored on t he tip of the stack. the address is decremented pri or to a push and incremented after a pop. the stack is also used as a return stack for calls and interrupts. during a call, the contents of the pc are saved on the stack to be restored later. interr upts cause the contents of the pc and flags to be s aved on the stack for recovery by iret when the interrup t is finished. when configured for internal stack (using the regis ter file), r217 contains the stack pointer. r216 ca n be used as a general purpose register. however, its co ntents will be changed if an overflow or underflow occurs as the result of incrementing or decrementin g the stack address during normal stack operations. a user-defined stack can be implemented in both the register file and program or data memory. these ca n be made to increment or decrement on a push by the choice of opcodes. for example, to implement a stack that goes from low addresses to high addresse s in the register file, use pushui and popud. for a stack that goes from high address to low addresses in data memory, use ldei for pop and ldepd for push. figure 14. r217 (d9) spl stack pointer bit 7 6 5 4 3 2 1 0 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w stack operations are supported in the register file or in data memory. bit 1 in the external memory ti ming register (r254b0) selects between the two. register pair r216-r217 forms the stack pointer use d for all stack operations. r216 is the msb and r217 is the lsb. the stack pointer always points to data stored on t he tip of the stack. the address is decremented pri or to a push and incrementd after a pop. the stack is also used as a return stack for calls and interrupts. during a call, the contents of the pc are saved on the stack to be restored later. interr upts cause the contents of the pc and flags to be s aved on the stack for recovery by iret when the interrup t is finished. when configured for internal stack (using the regis ter file), r217 contains the stack pointer. r216 ca n be used as a general purpose register. however, its co ntents will be changed if an overflow or underflow occurs as the result of incrementing or decrementin g the stack address during normal stack operations.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 23 of 80 1.888.824.4184 a user-defined stack can be implemented in both the register file and program or data memory. these ca n be made to increment or decrement on a push by the choice of opcodes. for example, to implement a stack that goes from low addresses to high addresse s in the register file, use pushui and popud. for a stack that goes from high address to low addresses in data memory, use ldei for pop and ldepd for push.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 24 of 80 1.888.824.4184 figure 15. instruction pointer high (iph), r218 bit 7 6 5 4 3 2 1 0 ip15 ip14 ip13 ip12 ip11 ip10 ip9 ipo8 initial value ? ? ? ? ? ? ? ? read/write r/w r/w r/w r/w r/w r/w r/w r/w a special register called the instruction pointer ( ip) provides hardware support for threaded-code languages. it consists of register-pair r218-r219 a nd contains memory addresses. the msb is r218. threaded-code languages deal with an imaginary high er-level machine within the existing hardware machine. the ip acts like the pc for that machine. the command next passes control to or from the hardware machine to the imaginary machine. and the commands enter and exit are imaginary machine equivalents of real machine calls and retur ns. if the commands next, enter and exit are not used, the ip can be used by the fast interrupt processing, as described in the interrupts section. figure 16. instruction pointer low (ipl), r219 bit 7 6 5 4 3 2 1 0 ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 initial value ? ? ? ? ? ? ? ? read/write r/w r/w r/w r/w r/w r/w r/w r/w a special register called the instruction pointer ( ip) provides hardware support for threaded-code languages. this register consists of register pair r218-r219 and contains memory addresses. the msb is r218. threaded-code languages deal with an imaginar y higher-level machine within the existing hardware machine. the ip acts like the pc for that machine. the command next passes control to or from the hardware machine to the imaginary machine. and the commands enter and exit are imaginary machine equivalents of real machine calls and returns. the ip can be used by the fast interrupt processing , as described in the interrupts section, if the co mmands next, enter and exit are not used. figure 17. interrupt mask (irm), r221 bit 7 6 5 4 3 2 1 0 level 7 level 7 level 7 level 7 level 7 level 7 level 7 level 7 initial value ? ? ? ? ? ? ? ? read/write r r r r r r r r
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 25 of 80 1.888.824.4184 when an interrupt in one of the 8 levels occurs and the corresponding mask bit is not set, the level b it of the interrupt is set to 1. the interrupt structure contains 8 levels of interrupt, 16 vectors and 27 s ources. interrupt priority is assigned by level and control led by the interrupt priority register (ipr) controlregr255b0. each level is masked (or enabled) according to the bits in the interrupt mask register (imr) systemregr221. each bit of the inter rupt mask register corresponds to one of the 8 levels of interrupts, irq register (systemregr220). when the corresponding bit in the interrupt mask register is set to one, that level interrupt is dis abled. figure 18. system mode register (sym), r222 bit 7 6 5 4 3 2 1 0 not used not used not used fis2 fsi1 fsi0 fse gie initial value ? ? ? ? ? ? ? ? read/write r/w r/w r/w r/w r/w r/w r/w r/w the fast interrupt select (fsi) selects which level interrupt can be treated as a fast interrupt. fast interrupt enable (fse), when set to 1, enables the selected level for fast interrupt. global interrupt enable (gie), when set to 1, enables interrupts in general . figure 19. halt mode register (hmr), r223 bit 7 6 5 4 3 2 1 0 not used not used not used not used d3 d2 d1 d0 initial value ? ? ? ? 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w d3 - cpu halt mode - writing a zero to this bit will invoke the halt mode upon the execution of the wfi instruction. the uart and counters can be halte d only if d3 is 0. during halt the internal cpu clock is disabled, and no address strobe is generat ed. a hardware reset sets this bit to a 1. d2 - disable uart - writing a zero to the bit will disable the uart. no interrupt request will be generated. a 1 will make the uart and its interrupt logic remain active in halt mode. a hardware reset forces this bit to a 1. d1 - disable ct1 - similar to ct0. when the counters are cascaded, the halt mode 32-bit counter is determined by the logical state of d1. a hardware r eset forces this bit to a 1. d0 - disable ct0 - writing a zero to this bit will disable the ct0 i n halt mode. no interrupt request will be generated in this case. a 1 will keep the c t0 active. a hardware reset forces this bit to a 1.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 26 of 80 1.888.824.4184 figure 20. counter 0 control register (c0ct), r224 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value x x 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w d0 - when this bit is set to 1, the counter/timer is e nabled. operation begins on the rising edge of the first processor clock period following the setting of thi s bit from a previously cleared value. writing a 1 in this field when the previous value was 1 has no effect o n the operation of the counter/timer. when this bit is cleared to 0, the counter/timer performs no operati on during the next (and subsequent) processor clock periods. a hardware reset forces this bit to 0. both counters are clocked by the rising edge of the incoming signal on p26 or p36 after the counter is enabled. the maximum frequency of the external cloc k signal applied to p36 (or p26) equals the maximum xtal frequency divided by 4. the maximum ga uaranteed xtal frequency is 20 mhz, which implies a maximum counter frequency of 5 mhz. d1 - reset/end of count status - this bit is set to 1 each time the counter reach es 0. writing a 1 to this bit resets it, while writing a 0 has no effect. d2 - zero count interrupt enable - when this bit is set to 1, the counter/timer gen erates an interrupt request when it counts to 0. a hardware reset force s this bit to 0. d3 - software capture - when this bit is set to 1, the current counter v alue is loaded into the capture register. this bit is automatically cleared followi ng the capture. d4 - software trigger - this bit is effectively "ored" with the external rising-edge trigger input and can be used by the software to force a trigger signal. this bit produces a trigger signal regardless of th e setting of the input pin assignment field of the mode regis ter. this bit is automatically cleared following th e trigger. d5 - load counter - the contents of the time constant register are t ransferred to the counter prescaler one clock period after this bit is set. this operat ion alone does not start the counter. this bit is automatically cleared following the load. d6 - count up/down - this bit determines the count direction if inter nal up/down control is specified in the mode register. 1 indicates up; 0 indicates down . d7 - continuous/single cycle - when this bit is set to 1, the counter is reload ed with the time-constant value when the counter reaches the end of the termi nal count. the terminal count for down counting is 0000, while the one for up counting is ffff. when t his bit is cleared to 0, no reloading occurs.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 27 of 80 1.888.824.4184 figure 21. counter 0 mode, r224 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value x x 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w d0 - when this bit is set to 1, the counter/timer is e nabled. operation begins on the rising edge of the first processor clock period following the setting of thi s bit from a previously cleared value. writing a 1 in this field when the previous value was 1 has no effect o n the operation of the counter/timer. when this bit is cleared to 0, the counter/timer performs no operati on during the next (and subsequent) processor clock periods. a hardware reset forces this bit to 0. both counters are clocked by the rising edge of the incoming signal on p26 or p36 after the counter is enabled. the maximum frequency of the external cloc k signal applied to p36 (or p26) equals the maximum xtal frequency divided by 4. the maximum ga uaranteed xtal frequency is 20 mhz, which implies a maximum counter frequency of 5 mhz. d1 - reset/end of count status - this bit is set to 1 each time the counter reach es 0. writing a 1 to this bit resets it, while writing a 0 has no effect. d2 - zero count interrupt enable - when this bit is set to 1, the counter/timer gen erates an interrupt request when it counts to 0. a hardware reset force s this bit to 0. d3 - software capture - when this bit is set to 1, the current counter v alue is loaded into the capture register. this bit is automatically cleared followi ng the capture. d4 - software trigger - this bit is effectively "ored" with the external rising-edge trigger input and can be used by the software to force a trigger signal. this bit produces a trigger signal regardless of th e setting of the input pin assignment field of the mode regis ter. this bit is automatically cleared following th e trigger. d5 - load counter - the contents of the time constant register are t ransferred to the counter prescaler one clock period after this bit is set. this operat ion alone does not start the counter. this bit is automatically cleared following the load. d6 - count up/down - this bit determines the count direction if inter nal up/down control is specified in the mode register. 1 indicates up; 0 indicates down . d7 - continuous/single cycle - when this bit is set to 1, the counter is reload ed with the time-constant value when the counter reaches the end of the termi nal count. the terminal count for down counting is 0000, while the one for up counting is ffff. when t his bit is cleared to 0, no reloading occurs.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 28 of 80 1.888.824.4184 figure 22. counter 0 mode, r225 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value x x 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w d0 - when this bit is set to 1, the counter/timer is enabled. operation begins on the rising edge of the first processor clock period following the setting of thi s bit from a previously cleared value. writing a 1 in this field when the previous value was 1 has no effect o n the operation of the counter/timer. when this bit is cleared to 0, the counter/timer performs no operati on during the next (and subsequent) processor clock periods. a hardware reset forces this bit to 0. both counters are clocked by the rising edge of the incoming signal on p26 or p36 after the counter is enabled. the maximum frequency of the external cloc k signal applied to p36(or p26) equals the maximum xtal frequency divided by 4. the maximum ga uaranteed xtal frequency is 20 mhz, which implies a maximum counter frequency of 5 mhz. d1 - reset/end of count status - this bit is set to 1 each time the counter reach es 0. writing a 1 to this bit resets it, while writing a 0 has no effect. d2 - zero count interrupt enable - when this bit is set to 1, the counter/timer gen erates an interrupt request when it counts to 0. a hardware reset force s this bit to 0. d3 - software capture - when this bit is set to 1, the current counter v alue is loaded into the capture register. this bit is automatically cleared followi ng the capture. d4 - software trigger - this bit is effectively "ored" with the external rising-edge trigger input and can be used by the software to force a trigger signal. this bit produces a trigger signal regardless of th e setting of the input pin assignment field of the mode regis ter. this bit is automatically cleared following th e trigger. d5 - load counter - the contents of the time constant register are t ransferred to the counter prescaler one clock period after this bit is set. this operat ion alone does not start the counter. this bit is automatically cleared following the load. d6 - count up/down - this bit determines the count direction if inter nal up/down control is specified in the mode register. 1 indicates up; 0 indicates down . d7 - continuous/single cycle - when this bit is set to 1 the counter is reloade d with the time-constant value when the counter reaches the end of the termi nal count. the terminal count for down counting is 0000, while the one for up counting is ffff. when t his bit is cleared to 0, no reloading occurs.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 29 of 80 1.888.824.4184 figure 23. counter 0 capture register (high byte) ( c0ch), r226 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w this 16-bit register pair is used to hold the count er value saved when using the "capture on external event" function. this register will capture at the rising edge of the i/o pin or when software capture is asserted. when the bi-value mode of operation is en abled, this register is used as a second time const ant register and the counter is alternately loaded from each. figure 24. counter 0 capture register (low byte) (c 0cl), r227 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w this 16-bit register pair is used to hold the count er value saved when using the "capture on external event" function. this register will capture at the rising edge of the i/o pin or when software capture is asserted. when the bi-value mode of operation is en abled, this register is used as a second time const ant register and the counter is alternately loaded from each. figure 25. counter 1 time constant register (high b yte) (c1cth), r228 bank 1 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w this 16-bit register pair holds the value that is a utomatically loaded into the counter/timer (1) when the counter/timer is enabled, (2) when the count reache s zero in continuous mode or (3) when the trigger i s asserted in re-trigger mode. if capture on both edg es is enabled, this register captures the contents of the counter on the falling edge of the i/o pin.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 30 of 80 1.888.824.4184 figure 26. counter 1 capture register (low byte) (c 1cl), r229 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 c1c7 C c1c0 initial value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w this 16-bit register pair is used to hold the count er value saved when using the "capture on external event" function. this register will capture at the rising edge of the i/o pin or when software capture is asserted. when the bi-value mode of operation is en abled, this register is used as a second time const ant register and the counter is alternately loaded from each. figure 27a. counter 0 prescaler (ctprs), r230 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 ct1 not used ct0 initial value 0 0 1 0 0 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w this register controls the source of the timer sign al when in internal mode. an 8-bit prescaler for ea ch counter is implemented. the control bit operate as follows: ct0/ct1 prescale 000 xtal/2 001 010 011 100 xtal/4 xtal/8 xtal/16 xtal/32 101 xtal/64 110 xtal/128 111 xtal/256 only the prescaler of ct1 is activated when the cou nters are cascaded.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 31 of 80 1.888.824.4184 figure 28b. watch dog timer and stop mode recovery register (wdt/smr) r230 bank0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 wdt time-out wdt enable wdt in stop wdt source smr on smr source initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w this register controls the watchdog timer time-out and stop recovery mode. d1, d0 stop mode recovery source select. bit d0 and d1 determine the stop mode recovery sour ce. d1 d0 0 0 recovery from reset only 0 1 recovery from p22 and reset 1 0 recovery from p32 and reset 1 1 recovery from any input for port 4 and reset a hardware reset forces d0 and d1 to zero. d2 stop recovery edge a 1 in this position indicates that a rising edge o n any one of the recovery sources wakes the ia88c00 from stop mode. a 0 indicates falling edge recovery . the reset value is 0. d3 xtal1/rc select for wdt when a zero is written to d3, the clock of the wdt is driven by the on-board rc oscillator. if d3 is s et to 1, the wdt is driven by xtal1. d3 has a zero reset value. d4 wdt enable during stop or halt when this bit is set, wdt is enabled during stop or halt. in this case, recovery from stop or halt should be performed before the selected time-out. a 0 in this bit location disables the wdt while the ia88c00 is stopped or halted. a hardware reset forc es this bit to a zero.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 32 of 80 1.888.824.4184 d5 wdt the watch-dog timer is initially enabled by writing a 1 to d5 and retriggered on subsequent writings t o the same bit. reset value = 0. writing a 0 to this bit has no effect. once a 1 is written to d5, it pe rsists until a hardware reset occurs. d6, d7 wdt time-out two sets of four different time-out values can be s elected, depending on the logical state of these bi ts. a normal reset signal must be active low during 5 x tal clock periods. using the reset signal input to recover from stop mode requires 10 xtal clock perio ds. this is so that xtal oscillation starts up and stabilizes, generating a good oscillator output lev el. the reset pin is held low in source during wdt time r time-out to accomplish a system reset with other peripherals of the super8. when the reset pin is he ld low, the capability of sink current via the rese t pin should be considered. (see dc characteristics.) figure 29. uart transmit control (utc), r235 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value 0 0 0 0 0 0 1 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w this register cont ains the status and command bit s needed to control the transmit sections of the ua rt. 0 - tdmaenb - transmit dma enable - when this bit is set to 1, the dma function for the uart transmit section is enabled. if this bit is set and the transmit buffer empty signal becomes true, a d ma request is made. when the dma channel gains control of the bus, it transfers bytes from the external memory or the register file to the uart transmit se ction. a hardware reset forces this bit to 0. d1 - tbe - transmit buffer empty - this status bit is set to 1 whenever the transmi t buffer is empty. it is cleared to 0 when a data byte is written in the transmit buffer. a hardware reset forces this bit t o 1. d2 - zc - zero count - this status bit is set to 1 and latched when the counter in the baud-rate generator reaches the count of 0. this bit can be cleared to 0 by writing a 1 to this bit position. a hardware r eset forces this bit to 0. d3 - tenb - transmit enable - data is not transmitted until this bit is set to 1. when cleared to 0, the transmit data pin continuously outputs 1s unless au to-echo mode is selected. this bit should be cleare d only after the desired transmission of data in the buffer is completed. a hardware reset forces this b it to 0.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 33 of 80 1.888.824.4184 d4 - wueb - wake-up enable - if this bit is set to 1, wake-up mode is enabled for both the transmitter and the receiver. the transmitter adds a bit beyond those specified by the bits/character and the pari ty. this added bit has the value specified in the trans mit wake-up value (twuval) in the uma register (controlregr250b0). the reveiver expects a wake-up bit value in the incoming data stream after the parity bit and compares this value with that specif ied in the received wake-up value (rwval) bit in th e uma register. the resulting action depends on the c onfiguration of the wake-up feature. d5 - stpbts - stop bits - this bit determines the number of stop bits added to each character transmitted from the uart transmit section. if this bit is a 0, one stop bit is added. if this bit is a 1, two stop bits are added. the receiver always checks for at least one stop bit. a hardware reset forces thi s bit to 0. d6 - senbrk - send break - when set to 1, this bit forces the transmit secti on to continuously output 0s, beginning with the following transmit clock, re gardless of any data being transmitted at the time. this bit functions whether or not the transmitter is ena bled. when this bit is cleared to 0, the transmit s ection continues to send the contents of the transmit data register. a hardware reset forces this bit to 0. d7 - txdtsel - transmit data selec t - this bit has an effect only if port pin p31 is configured as an output. if this bit is set to 1, the serial data co ming out of the transmit section is reflected on th e p31 pin. if this bit is set to 0, p31 acts as a normal port and p31 data is reflected on the p31 pin. a hardwar e reset forces this bit to 0. figure 30. uart receive control (urc), r236 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r d0 - rca - receive character available - this is a status bit that is set to a 1 when dat a is available in the receive buffer (uior). when the cpu reads the r eceive buffer, it automatically clears this bit to 0. a write to this possition has not effect. a hardware reset forces this bit to 0. d1 - renb - receive enable - when this bit is set to 1, the receive operation begins. this bit should be set only after all other receive parameters are est ablished and the reciver is completely initialized. a hardware reset clears this bit to 0. d2 - perr - parity error - this is a status bit. when parity is enabled, th is bit is set to 1 and buffered with the character whose parity does not match the programmed parity (even/odd). this bit is latched s o that once an error occurs, it remains set until it is cleared to 0 by writing a 1 to this bit position . d3 - overr - overrun error - this status bit indicates that the receive buffe r has not been read and another character has been received. only the chara cter that has been written over is flagged with thi s error. once set, this bit remains set until cleared to 0 by writing a 1 to this bit position.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 34 of 80 1.888.824.4184 d4 - ferr - framing error - this is a status bit. if a framing error occurs (no stop bit where expected), this bit is set for the receive character in which the framing error occurred. this bit remains set un til cleared to 0 by writing a 1 to this bit position. d5 - brkd - break detect - this is a status bit that is set at the beginnin g and the end of a break sequence in the receive data stream. it stays set t o 1 until cleared to 0 by writing a 1 to this bit p osition. a break signal is a sequence of 0s. when all the re quired bits, parity bit, wake-up bit, and stop bits are 0x, the receiver immediately recognizes a break conditi on (not a framing error) and causes break detect (brkd) to be set and an interrupt request. at the e nd of the break signal, a zero character is loaded into the receive data register (uior) and break detect i s set again, along with another interrupt request. d6 - ccd - control character detect - this status bit is set any time an ascii control character is received in the receive data stream. it stays set u ntil cleared to 0 by writing a 1 to this bit positi on. (an ascii control character is any character that has b its 5 and 6 set to 0.) d7 - wud - wake-up detect - this status bit is set any time a valid wake-up condition is detected at the receiver. it stays set until cleared to 0 by writin g a 1 to this bit position. the wake-up condition c an be satisfied in many possible ways by the wake-up bit, wake-up match register, and wake-up mask register. figure 31. uart interrupt enable (uie), r237 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w d0 - rcaie - receive character available interrupt enable - if this bit is set to 1, a receive character available status in the urc register will cause an interrupt request. in a dma receive operation, if this bit is set to 1, an interrupt re quest will be issued only if an end-of-process (eop ) of the dma counter is also set. if it is not set, a receiv e character available status causes no interrupt. d1 - rdmaenb - receive dma enabl e - when this bit is set to 1, the dma function is enabled for the uart receiver. whenever a receive character availab le signal in the urc register is true, a dma request will be made. when the dma channel claims c ontrol of the bus, it transfers the received data t o the register file or the external memory. d2 - tie - tranmit interrupt enable - if this bit is set to 1, a transmit buffer empty signal in the utc register will cause an interrupt request. in a dma transmit operation, if this bit is set to 1, an int errupt request will be issued only if an end-of-process (e op) of the dma counter is also set. if it is not se t, a transmit buffer empty signal causes no interrupt. d3 - zcie - zero count interrupt enable - if this bit is set to 1, a baud-rate generator z ero count status in the utc register will cause an interrupt request.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 35 of 80 1.888.824.4184 d4 - reie - receive error interrupt enable - if this bit is set to 1, any receiver error cond ition will cause an interrupt request. possible receive error conditions include parity error, overrun error and framing error. d5 - brkie - break interrupt enable - if this bit is set to 1, a transition in either direction on the break signal will cause an interrupt request. d6 - ccie - control character interrupt enabl e - if this bit is set to 1, an ascii control chara cter detect signal in the urc register will cause an int errupt. d7 - wuie - wake-up interrupt enable - if this bit is set to 1, any of the wake-up cond itions that set the wake-up detect bit (wud) in the urc register wi ll cause an interrupt request. figure 32. uart transmit interrupt register, uti r2 38 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value 0 0 0 0 0 0 1 0 read/write r/w r/w r/w r/w r/w r/w r/o r/w the timing for the transmit buffer empty interrupt is software programmable. there are two different interrupt timings selectable with 1 bit. option 1: interrupt is activated at the moment the contents of the tuio register are transferred to the tx fifo. option 2: interrupt is activated at the moment the last stop bit in the tx fifo is sent. after loading the transmit shift register, uart con trol generates a buffer empty flag to indicate that tuio is ready to be filled with new data. a new flag will indicate when the transmit shift re gister is empty. d0 - if this bit is zero, a high value of d2 in the u ie register will cause an interrupt on transmit uio empty. if this bit is set, a high value of d2 in th e uie register will cause an interrupt on transmit shift register empty. that is when the last stop bit is t ransmitted. this bit should be programmed prior to writing to the uio register. d1 - this flag is set when the transmit shift registe r is empty and is reset when a new value is loaded into the uio. this flag will not be set during a send br eak. figure 33. uart data register (uio), r239 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/o r/w
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 36 of 80 1.888.824.4184 writing to this register automatically writes the d ata in the transmit data register (uiot). a read fr om this register gets the data from the uart receive d ata register (uior).
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 37 of 80 1.888.824.4184 figure 34. port 0 mode control register (p0m), r240 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value 0 0 0 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w the port 0 mode register programs each bit of port 0 as an address output (part of an external memory interface) or as an i/o bit. when a bit of this reg ister is 1, the corresponding bit of port 0 is defi ned as an address output. when 0, the corresponding bit of po rt 0 is defined as an i/o bit. d0-d7 - p00-p07 mode , 0 = i/o, 1 = address. figure 35. port mode register (pm), r241 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value x x 1 0 0 0 0 1 read/write ? ? ? ? ? ? ? ? the port mode register provides some additional mod e control for ports 0 and 1. d0 - port 0 direction - if this bit is a 1, all bits of port 0 configure d as i/o will be inputs. if this bit is a 0, the i/o lines will be outputs. d1 - open-drain port 0 - if this bit is a 1, all bits of port 0 configure d as outputs will be open-drain outputs. if 0, they will be push-pull outputs. this bit has no effect on those bits not configured as outputs. d2 - open-drain port 1 - if port 1 is configured as an output port and th is bit is a 1, all of the port will be open-drain outputs. if this bit is a 0, they wil l be push-pull outputs. this bit has no effect if p ort 1 is not configured as an output port or a/d 0-7. d3 - enable /dm - if this bit is a 1, port 35 is configured as dat a memory output line /dm. d4-d5 - this field selects the configuration of port 1 a s an output port, input port, or address/data port as part of the external memory interface. figure 36. handshake 0 control (h0c), r244 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value x x x x x 0 x 0 read/write w/o w/o w/o w/o w/o w/o w/o w/o this register controls handshake channel 0.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 38 of 80 1.888.824.4184 d0 - handshake enable - when this bit is set to 1, the handshake functio n is enabled. d1 - port select - this bit selects which port is controlled by han dshake channel 0. when it is set to 1, port 1 is selected and when it is cleared to 0, por t 4 is selected. d2 - dma enable - when this bit is set to 1, the dma function is e nabled for handshake channel 0. when it is cleared to 0, the dma function is not us ed by the handshake channel and may be used by the uart. d3 - mode - when this bit is set to 1, the "fully interlocke d" mode is enabled. when it is cleared to 0, the "strobed" mode is enabled. d4-d7 - deskew count er - this 4-bit field is used to select a count val ue from 1 to 16 (0000-1111). this value is the number of processor clocks used to gen erate the set-up and strobe when using the "strobed " mode, or the set-up when using the "fully-interlock ed" mode. figure 37. handshake 1 control (h1c), r245 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value x x x x x x x 0 read/write w/o w/o w/o w/o w/o w/o w/o w/o this register controls handshake channel 1. d0 - handshake enable - when this bit is set to 1, the handshake functio n is enabled. d1 - not used. d2 - not used. d3 - mode - when this bit is set to 1, the "fully interlocke d" mode is enabled. when it is cleared to 0, the "strobed" mode is enabled. d4-d7 - deskew counte r - this 4-bit field is used to select a count valu e from 1 to 16 (0000-1111). this value is the number of processor clocks used to gen erate the set-up and strobe when using the "strobed " mode, or the set-up when using the "fully-interlock ed" mode. figure 38. port 4 direction control register (p4d), r246 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 39 of 80 1.888.824.4184 the port 4 direction register defines the i/o direc tion of port 4 on a bit basis. if a bit of this reg ister is a 1, the corresponding bit of port 4 is configured as an d input line. if the bit is a 0, the corresponding bit of port 4 is configured as and output line. d0-d7 - p40-p47 mode, 0 = output, 1 = input.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 40 of 80 1.888.824.4184 figure 39. port 4 open-drain (p4od), r247 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value 0 0 0 0 0 0 0 0 read/write ? ? ? ? ? ? ? ? the port 4 open-drain register defines the output d river type for port 4. if a bit of port 4 has been configured as an output and the corresponding bit i n the port 4 open-drain register is a 1, the port 4 bit will have an open-drain output driver. if it is a 0 , the port 4 bit will have a push-pull output drive r. if the bit of port 4 has been configured as an input, the corresponding bit is the port 4 open-drain register has no effect. figure 40. port 4 open-drain (p4od), r247 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value 0 0 0 0 0 0 0 0 read/write w/o w/o w/o w/o w/o w/o w/o w/o the port 2/3 a mode, port 2/3 b mode, port 2/3 c mo de and port 2/3 d mode registers control the modes of ports 2 and 3. a separate 2-bit field for each of the bits of ports 2 and 3 configures the bi t as input or output. the field also controls whether th e bit is enabled as an external interrupt source an d selects the oputpus as open-drain or push-pull. figure 41. port 2/3 a mode register, r248 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value 0 0 0 0 0 0 0 0 read/write w/o w/o w/o w/o w/o w/o w/o w/o the port 2/3 a mode, port 2/3 b mode, port 2/3 c mo de and port 2/3 d mode registers control the modes of ports 2 and 3. a separate 2-bit field for each of the bits of ports 2 and 3 configures the bi t as input or output. the field also controls whether th e bit is enabled as an external interrupt source an d selects the oputpus as open-drain or push-pull.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 41 of 80 1.888.824.4184 figure 42. port 2/3 b mode register, r249 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value 0 0 0 0 0 0 0 0 read/write w/o w/o w/o w/o w/o w/o w/o w/o the port 2/3 a mode, port 2/3 b mode, port 2/3 c mo de and port 2/3 d mode registers control the modes of ports 2 and 3. a separate 2-bit field for each of the bits of ports 2 and 3 configures the bi t as input or output. the field also controls whether th e bit is enabled as an external interrupt source an d selects the oputpus as open-drain or push-pull. figure 43. port 2/3 c mode register, r250 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value 0 0 0 0 0 0 0 0 read/write w/o w/o w/o w/o w/o w/o w/o w/o the port 2/3 a mode, port 2/3 b mode, port 2/3 c mo de and port 2/3 d mode registers control the modes of ports 2 and 3. a separate 2-bit field for each of the bits of ports 2 and 3 configures the bi t as input or output. the field also controls whether th e bit is enabled as an external interrupt source an d selects the oputpus as open-drain or push-pull. figure 44. port 2/3 d mode register, r251 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value 0 0 0 0 0 0 0 0 read/write w/o w/o w/o w/o w/o w/o w/o w/o the port 2/3 a mode, port 2/3 b mode, port 2/3 c mo de and port 2/3 d mode registers control the modes of ports 2 and 3. a separate 2-bit field for each of the bits of ports 2 and 3 configures the bi t as input or output. the field also controls whether th e bit is enabled as an external interrupt source an d selects the oputpus as open-drain or push-pull.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 42 of 80 1.888.824.4184 figure 45. port 2/3 a interrupt pending register (p 2aip), r252 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value 0 0 0 0 0 0 0 0 read/write ? ? ? ? ? ? ? ? read only (writeable for reset puposes) the port 2/3 a interrupt pending and port 2/3 b int errupt pending registers represent the software interface to the negative edge-triggered flip-flops associated with external interrupt inputs. each bi t of these registers corresponds to an interrupt generat ed by an external source. when one of these registe rs is read, the value of each bit represents the state of the corresponding interrupt. when one of these reg isters is written to, a 1 in a bit position causes the cor responding edge-triggered flip-flop to be reset to 0. a 0 causes no action. the software interfaces with these registers to pol l the interrupts and also to reset pending interrup ts as they are processed. figure 45 shows the pin relatio nship. figure 46. port 2/3 b interrupt pending register (p 2bip), r253 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value 0 0 0 0 0 0 0 0 read/write ? ? ? ? ? ? ? ? read only (writeable for reset puposes) the port 2/3 a interrupt pending and port 2/3 b int errupt pending registers represent the software interface to the negative edge-triggered flip-flops associated with external interrupt inputs. each bi t of these registers corresponds to an interrupt generat ed by an external source. when one of these registe rs is read, the value of each bit represents the state of the corresponding interrupt. when one of these reg isters is written to, a 1 in a bit position causes the cor responding edge-triggered flip-flop to be reset to 0. a 0 causes no action. the software interfaces with these registers to pol l the interrupts and also to reset pending interrup ts as they are processed. figure 46 shows the pin relatio nship.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 43 of 80 1.888.824.4184
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng 21 0 050519-00 www.inn ovasic innovasic.com innovasic semiconductor page 44 of 80 1.888.824.4184 figure 47. external memory timing register, r254 ba nk 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value 1 0 0 0 0 0 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w this register controls all the extended bus timing features. d0 - dma select - if 0, dma uses register file space. if 1, it use s data memory. d1 - stack select - if 0, stack is located in register file space. i f 1, it is located in data memory. figure 48. interrupt priority register (ipr), r255 bank 0 bit 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w the interrupt priority register defines the priorit y order of the interrupt levels. interrupts should be globally disabled before writing to this register. d0 - group a - 0=irq0 > irq1; 1=irq1 > irq0. d2 - group b - 0=irq2>(irq3,irq4); 1=(irq3,irq4) > ir q2. d3 - subgroup b - 0=irq3>irq4; 1=irq4>irq3. d5 - group c - 0=irq5>(irq6,irq7); 1=(irq6,irq7)>irq5 . d6 - subgroup c - 0=irq6>irq7; 1=irq7>irq6.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 45 of 80 1.888.824.4184 instruction summary this section provides a summary of the ia88c00 inst ructions. note assignment of a value is indicated by the symbol . for example: dst dst + src indicates that the source data is added to the dest ination data and the result is stored in the destin ation location. the notation addr (n) is used to refer to bit (n ) of a given operand location. for example: dst (7) refers to bit 7 of the destination operand. figure 49. instruction summary flags affected instruction and operation address mode dst scr opcode byte (hex) c z s v d h adc dst, src dstdst + src + c ? 1[ ] * * * - 0 * add dst, src dstdst + src ? 0[ ] * * * * 0 * add dst, src dstdst and src ? 5[ ] - * * 0 - - band dst, src dstdst and src r0 rb rb r0 67 67 - * 0 u - - bcp dst, src dst - src r0 rb 17 - * 0 u - - bitc dst dstnot dst rb 57 - * 0 u - - bitr dst dst0 rb 77 - - - - - - -
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 46 of 80 1.888.824.4184 flags affected instruction and operation address mode dst scr opcode byte (hex) c z s v d h bits dst dst0 dst1 rb 77 - - - - - - - flags affected instruction and operation address mode dst scr opcode byte (hex) c z s v d h bor dst, src dst0 or src r0 rb 07 - * 0 u - - btjrf dst0 if src=0, pc=pc+dst ra rb 37 - - - - - - btjrt if src=0, pc=pc+dst ra rb 37 - - - - - - bxor dst, src dstdst xor src r0 rb 27 - * 0 u - - call dst spsp - 2 @sppc, pcdst da irr ia f6 f4 d4 - - - - - - ccf cnot c ef * - - - - - clr dst dst0 r ir b0 b1 - - - - - - com dst dstnot dst r ir 60 61 - * * 0 - - cp dst, src dst - src ? a[ ] * * * * - - cpije if dst - src=0, then pcpc+ra irir + 1 r ir c2 - - - - - - cpijne if dst - src=0, then pcpc+ra irir + 1 r ir d2 - - - - - - da dst dstda dst r ir 40 41 * * * u - - dec dst dstdst - 1 r ir 00 01 - * * * - -
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 47 of 80 1.888.824.4184 decw dst dstdst - 1 rr ir 80 81 - * * * - - di smr(0)0 8f - - - - - - div dst, src dstsrc rr r 94 * * * * - - dst (upper) rr ir 95 quotient dst (lower) rr im 96 remainder flags affected instruction and operation address mode dst scr opcode byte (hex) c z s v d h djnz r, dst ra r ra - - - - - - rr - 1 (r=0 iof) if r = 0 pcpc + dst el smr(0) 9f - - - - - - enter spsp - 2 @ spip ippc pc@ ip ipip + 2 1f - - - - - - exit ip@sp spsp + 2 pc@ ip ipip + 2 2f - - - - - - inc dst r re - * * * - - dstdst + 1 r=0-f r 20 ir 21 incw dst rr a0 - * * * - - dstdst + 1 ir a1 iret (fast) bf restored to pc?ip flagflag fis0 before interrupt
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 48 of 80 1.888.824.4184 iret (normal) bf restored to flags@sp; before interrupt spsp + 1; pc@ sp spsp + 2; smr(0) 1 jp cc, dst da ccd - - - - - - if cc is true c = 0 to f pcdst irr 30 jr cc, dst ra ccb - - - - - - if cc is true, cc = 0 to f pcpc + d ld dst, src r im rc - - - - - - dstsrc r r r8 r r9 r = 0 to f flags affected instruction and operation address mode dst scr opcode byte (hex) c z s v d h r ir c7 ir r d7 r r e4 r ir e5 r im e6 - ir im d6 ir r f6 r x 87 - x r 97 ldb dst, src r0 rb 47 - - - - - dstsrc rb r0 47 - ldc/lde r lrr c3 - - - - - - dstsrc lrr r d3 r xs e7 xs r f7 r x1 a7 x1 r b7 r da a7 da r b7 ldcd/lded dst, src r lrr e2 - - - - - - dstsrc rrrr-1 ldei/ldci dst, src r lrr e3 - - - - - - dstsrc rrrr+1 ldcpd/ldci dst, src r lrr e3 - - - - - -
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 49 of 80 1.888.824.4184 dstsrc rrrr+1 ldcpi/ldepi dst, src r lrr e3 - - - - - - dstsrc rrrr+1 ldw dst, src rr rr c4 - - - - - - rr ir c5 rr imm c6 mult dst, src rr r 84 * 0 * * - - rr ir 85 rr im 86 next 0f - - - - - - pc@ ip ipip + 2 nop ff - - - - - - or dst, src ? 4[ ] - * * 0 - - dstdst or src pop dst r 50 - - - - - - dst@sp; ir 51 spsp + 1 popud dst, src r ir 92 - - - - - - dstsrc irir - 1 popui dst, src r ir 93 - - - - - - dstsrc irir + 1 - flags affected instruction and operation address mode dst scr opcode byte (hex) c z s v d h push scr r 70 - - - - - - spsp - 1; @spsrc ir 71 pushud dst, src ir r 82 - - - - - - irir - 1 dstsrc pushui dst, src ir r 83 - - - - - - irir + 1 dstsrc rcf cf 0 - - - - - c0 ret pc@sp;spsp+2 af - - - - - - rl dst r 90 * * * * - - cdst(7) ir 91 dst(0)dst(7)
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 50 of 80 1.888.824.4184 dst(n+1)dst(n) n=0 to 6 rlc dst r 10 * * * * - - dst(0)c ir 11 cdst(7) dst(n)dst(n+1) n=0 to 6 rr dst r c0 * * * * - - cdst(0) ir c1 dst(7)c dst(n)dst(n+1) n=0 to 6 sb0 4f - - - - - - bank0 sb1 5f bank1 sbc dst, src ? 3[ ] * * * * 1 * dstdst - src - c scf df 1 - - - - - c1 sra dst r d0 * * * 0 - - dst(7)dst(7) cdst(0) dst(n)dst(n+1) n=0 to 6 srp src im 31 - - - - - - rp0im rp1im+8 srp0 im 31 - - - - - - rp0im srp1 im 31 - - - - - - rp1im stop 6f - - - - - - sub dst, src ? 2[ ] * * * * 1 * dstdst - src swap dst r f0 - * * u - - dst(0-3)?dst(4-7) ir f1 tcm dst, src ? 6[ ] - * * 0 - - (not dst) and src tm dst, src ? 7[ ] - * * 0 - - dst amd src tsw dst, src r r 7f u * * 0 u u wfi 3f - - - - - - xor dst, src ? b[ ] - * * 0 - -
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 51 of 80 1.888.824.4184 dstdst xor src ? these instructions have an identical set of addre ssing modes, which are encoded for brevity. the fir st opcode nibble is found in the instruction set table above. the second nibble is e xpressed symbolically by a [ ] in this table. its value is found in the following table to the left of the applicable addressing mode pair. for example, the opcode of an adc instruction using the addressing modes r (destination) and ir (sourc e) is 13. address dst mode src lower opcode nibble r r [2] r ir [3] r r [4] r ir [5] r im [6] notes: 0 = cleared to zero 1 = set to one C = unaffected * = set or reset, depending on result of operation . u = undefined
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 52 of 80 1.888.824.4184 opcode map figure 50. opcode map lower nibble (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 6 dec r 1 6 dec r 2 6 add r 1 r 2 6 add r 1 ir 2 10 add r 2 r 1 10 add ir 2 r 1 10 add r 1 im 10 bor r 0 r b 14 next 1 6 rlc r 1 6 rlc ir 1 6 adc r 1 r 2 6 adc r 1 ir 2 10 adc r 2 r 1 10 adc ir 2 r 1 10 adc r 1 im 10 bcp r 1 b r 2 20 next 2 6 inc r 1 6 inc ir 1 6 sub r 1 r 2 6 sub r 1 ir 2 10 sub r 2 r 1 10 sub ir 2 r 1 10 sub r 1 im 10 bxor* r 0 r b 22 exit 3 10 jp irr 1 note c 6 sbc r 1 r 2 6 sbc r 1 ir 2 10 sbc r 2 r 1 10 sbc ir 2 r 1 10 sbc r 1 im note a 6 wfi 4 6 da r 1 6 da ir 1 6 or r 1 r 2 6 or r 1 ir 2 10 or r 2 r 1 10 or r 2 r 1 10 or r 1 im 10 ldb* r 0 r b 6 sbo 5 10 pop r 1 6 pop ir 1 6 and r 1 r 2 6 and r 1 ir 2 10 and r 2 r 1 10 and ir 2 r 1 10 and r 1 im 8 bitc r 1 b 6 sbi 6 6 com r 1 6 com ir 1 6 tcm r 1 r 2 6 tcm r 1 ir 2 10 tcm r 2 r 1 10 tcm ir 2 r 1 10 tcm r 1 im 10 band* r 0 r b 6 stop 7 10/12 push r 2 10/14 push ir 2 6 tm r 1 r 2 6 tm r 1 ir 2 10 tm r 2 r 1 10 tm ir 2 r 1 10 tm r 1 im note b 10 tsw rr 8 10 decw rr 1 10 decw ir 1 10 pushud ir 1 r 2 10 pushui ir 1 r 2 24 mult r 2 rr 1 24 mult ir 2 rr 1 24 mult im 2 rr 1 10 ld r 1 xr 2 6 di 9 6 rl r 1 6 rl ir 1 10 popud ir 2 r 1 10 popui ir 1 r 2 28/12 div r 2 rr 1 28/12 div ir 2 rr 1 28/12 div imrr 1 10 ld r 1 xr 1 6 ei a 10 incw rr 1 10 incw ir 1 6 cp r 1 r 2 6 cp r 1 ir 2 10 cp r 2 r 1 10 cp ir 2 r 1 10 cp r 1 im note d 14 ret b 6 clr r 1 6 clr ir 1 6 xor r 1 r 2 6 xor r 1 ir 2 10 xor r 2 r 1 10 xor ir 2 r 1 10 xor r 1 im note e 16/6 iret c 6 rrc r 1 6 rrc ir 1 16/18 cpije irr 2 ra 12 ldc* r 2 irr 1 10 ldw rr 2 rr 1 10 ldw ir 2 rr 1 12 ldw rr 1 iml 6 ld r 1 ir 2 6 rcf d 6 sra r 1 6 sra ir 1 16 cpijne ir 1 r 2 ra 12 ldc* r 2 irr 1 20 call ia 1 10 ld ir 1 im 6 ld ir 1 r 2 6 scf e 6 rr r 1 6 rr ir 1 16 ldcd* r 1 irr 2 16 ldcd* r 1 irr 2 10 ld r 2 r 1 10 ld ir 2 r 1 10 ld r 1 im 18 ldc* r 1 irr 2 xs 6 ccf f 8 swap r 1 8 swap ir 1 16 ldcpd* r 2 irr 1 16 ldcpi* r 2 irr 1 18 call irr 1 10 ld r 2 ir 1 18 call da 1 18 ldc* r 2 irr 1 xs 6 ld r 1 r 2 6 ld r 2 r 1 12/10 djnz r 1 ra 12/10 jr ccra 6 ld r 1 im 12/10 jp ccda 6 inc r 1 6 nop
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 53 of 80 1.888.824.4184 note a 16/18 btjrf r 2 bra 16/18 btjrf r 2 bra note b 8 bits r 1 b 8 bits r 1 b note c 6 srp im 6 srp0 im 6 srp1 im legend: r = 4-bit address r = 8-bit address b = bit number r 1 or r 1 = dst address r 2 or r 2 = src address examples: bor r 0 r 2 is bor r 1 tr 1 or bor r 2 br 1 ldc r 1 irr 2 is ldc r 1 irr 2 = program or lde r 1 irr 2 = date note d 20 ldc r 1 irr 2 xl 20 ldc r 1 da 2 note e 20 ldc r 2 irr 2 xl 20 ldc r 2 da 1 sequence: opcode, first, second, third operands note: the blank areas are not defined. instructions figure 51. load instructions mnemonic operands instructions clr dst clear ld dst, src load ldb dst, src load bit ldc dst, src load program memory lde dst, src load data memory ldcd dst, src load program memory and decrement lded dst, src load data memory and decrement ldci dst, src load program memory and increment ldei dst, src load data memory and increment ldcpd dst, src load program memory with pre-decreme nt ldepd dst, src load data memory with pre-decrement ldcpi dst, src load program memory with pre-increme nt ldepi dst, src load data memory with pre-increment ldw dst, src load word pop dst pop stack popud dst, src pop user stack (decrement) popui dst, src pop user stack (increment) push src push stack pushud dst, src push user stack (decrement) pushui dst, src push user stack (increment) figure 52. arithmetic instructions mnemonic operands instructions adc dst, src add with carry add dst, src add cp dst, src compare da dst decimal adjust dec dst decrement decw dst decrement word div dst, src divide inc dst increment
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 54 of 80 1.888.824.4184 incw dst increment word mult dst, src multiply sbc dst, src subtract with carry sub dst, src subtract
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 55 of 80 1.888.824.4184 figure 53. logical instructions mnemonic operands instructions and dst, src logical and com dst complement or dst, src logical or xor dst, src logical exclusive figure 54. program control instructions mnemonic operands instructions btjrt dst, src bit test jump relative on true btjrf dst, src bit test jump relative on false call dst call procedure cpije dst, src compare, increment and jump on equal cpijne dst, src compare, increment and jump on non- equal djne r, dst decrement and jump on non-zero enter enter exit exit iret return from interrupt jp cc, dst jump on condition code jp dst jump unconditional jr cc, dst jump relative on condition code jr dst jump relative unconditional next next ret return wfi wait for interrupt figure 55. bit manipulation instructions mnemonic operands instructions band dst, src bit and bcp dst, src bit compare bitc dst bit complement bitr dst bit reset bits dst bit set bor dst, src bit or bxor dst, src bit exclusive or tcm dst, src test complement under mask tm dst, src test under mask tsw src1, src2 test word
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 56 of 80 1.888.824.4184 figure 56. rotate and shift instructions mnemonic operands instructions rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry swap dst swap nibbles figure 57. cpu control instructions mnemonic operands instructions ccf complement carry flag di disable interrupts ei enable interrupts nop do nothing rcf reset carry flag sbo set bank flag sb1 set bank 1 scf set carry flag srp src set register pointers srp0 src set register pointer zero srp1 src set register pointer one stop enable stop mode interrupts the ia88c00 supports as many as 27 interrupt source s. interrupt sources are sorted into 8 different priority levels. these levels are controlled by the interrupt priority register (ipr). enabling and ma sking of individual interrupts is controlled by the syste m mode register (r222). the various sources, vectors and levels of the inte rrupt structure are depicted in figure 58 in this s ection.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 57 of 80 1.888.824.4184 interrupt sources polling vectors levels counter 0 zero count external interrupt (p2 6 ) external interrupt (p2 7 ) counter 1 zero count external interrupt (p3 6 ) external interrupt (p3 7 ) handshake channel 0 external interrupt (p2 4 ) external interrupt (p2 5 ) handshake channel 1 external interrupt (p3 4 ) external interrupt (p3 5 ) reserved reserved external interrupt (p3 2 ) external interrupt (p2 2 ) external interrupt (p3 2 ) external interrupt (p2 2 ) uart receive overrun uart framing error uart parity error uart wakeup detect uart break detect uart control char detect uart receive data external interrupt (p3 0 ) external interrupt (p2 0 ) uart zero count external interrupt (p2 1 ) uart transmit data external interrupt (p3 1 ) 12 14 28 30 02 4 6 8 10 16 18 20 22 24 26 irq2 irq5 irq4 irq7 irq3 irq0 irq6 irq1 figure 58. interrupt levels and vectors
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 58 of 80 1.888.824.4184 interrupt programming model the ia88c00 maintains program compatibility with th e super8. enabling or disabling of interrupts are controlled via the following registers: interrupt enable/disable . see the system mode register (r222). level enable. see the interrupt mask register (r221). level priority. see the interrupt priority register (r255, bank 0) . source enable/disable. interrupt sources are enabled or disabled in the individual sources mode and control register. functional overview for an interrupt to be serviced, its source must b e enabled. the corresponding interrupt and level mu st likewise be enabled. each interrupt input is condit ioned with edge-triggered devices to convert all interrupt inputs to levels. the eliminates the re quirement for external hardware to maintain the int errupt input prior to servicing. when an interrupt source is received the processor is vectored to the vector address associated with the interrupt. in the fact of multiple interrupts, the enabled interrupt whose level has the highest prior ity is serviced first. for interrupts within the same leve l, the priority of the individual interrupt takes precedence. upon servicing the interrupt, the processor clears the interrupt enable bit in the system mode registe r to prevent a high priority interrupt from disrupting t he service routine. the program counter and status flags are pushed onto the stack and the program counter i s loaded with the appropriate interrupt vector and the interrupt service routine (isr) begins to the execu te. upon completion, the isr executes an ret instruction. the flags and program counter are popp ed off the stack and the interrupt enable bit in th e system mode register is set. the ia88c00 supports a special mode of fast inter rupt processing. utilization of this mode requires program intervention. the vector address of the isr must be loaded into the instruction pointer and th e fast interrupt enable bit in the system mode regist er must be set. upon receipt of the interrupt sourc e, the isr vector is loaded into the program counter w hile the old value of the program counter is saved in the instruction pointer. status flags are saved in the flags register and the fast interrupt status bi t in flags is set. upon completion of the isr, the proce ss is reversed. stack operation the ia88c00 maintains program model compatibility o n all stack operations. the stack may be maintained in either the register file or in data m emory space. for programming model details see registers r216/r217 (the stack pointer) and registe r r254 (memory timing register)
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 59 of 80 1.888.824.4184 the ia88c00 also supports user-defined stacks. thes e stacks are accessed via the pushui, popud, ldei and ldepd instructions. counter/timers the ia88c00 provides two identical 16 bit timer/cou nters with an 8-bit prescaler. the counters are dri ven from a divide-by-4 clock derived from the oscillato r. each count provides robust functionality includi ng: ? up or down count ? single or continuous count ? output pulse train with variable duty cycle ? input capture ? external gating/triggering for longer events, the counters may be cascaded to form a 32-bit counter. for program model details se e registers r224 through r230. dma the ia88c00 supports high speed data transfer suppo rt for the uart and handshake channel 0 via direct memory access (dma). data can be transferred between these peripherals and contiguous locations in either the register file or external d ata memory. for details on the programming model se e registers r235 (uart transmit control) r236 (uart r eceive control), r244 (handshake channel 0 control) and r240/241, bank 1 (dma count). wdt the ia88c00 provides a watchdog (wdt) timer to pr ovide sanity checks on the processor. should program execution hang, the wdt timeout will expire and the reset pin will be held active for 5 ms. the wdt is prevented from timing out by periodicall y writing a 1 to bit d5 in the wdt/smr register. the wdt clock is derived from either an internal ri ng oscillator or from the crystal oscillator input. it should be noted that the frequency of the internal oscillator and associated wdt time-out can vary wid ely (as much as 3 times) with voltage and temperature. for details on the wdt programming model see register r230 (wdt/smr register). stop mode when a stop instruction is executed, the process en ter stop mode. during stop mode, the system clock and external oscillator are disabled. stop mode is exited via a hard reset, or by applying an edge to a pre- defined bit of either port 2, 3, or 4. for details on the stop mode programming model see register r2 30 (wdt/smr register).
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 60 of 80 1.888.824.4184 halt mode when the ia88c00 execute the wait for interrupt (wf i) instruction and bit 3 of r223 (halt mode register) is cleared, the processor enters halt mod e. the internal cpu clock is disabled, however, the oscillator remains active. use of the uart, timers and dma remains under user control. the halt mode is exited via an interrupt or dma request. the prog ramming model for halt mode is detailed in r223 (halt mode register)
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 61 of 80 1.888.824.4184 i/o ports the ia88c00 contains 40 i/o lines arranged into fiv e 8-bit ports. each line is ttl-compatible and can be configured as a address/data line. each port inclu des an input register, an output register and a reg ister address. the input register stores data coming into the port. the output register stores data to be wr itten to a port. reading a ports register address returns the value in the input register. writing a ports r egister address loads the value in the output register. if the port is configured for an output, this value wi ll appear on the external pins. when the cpu reads the bits configured as outputs, the data on the external pins is returned. under normal output loading, this has the same effect as reading the output register, unless the bits are configured as open-drain outputs. the ports can be configured as shown in figure 59. figure 59. port configuration port configuration choices 0 high address and/or 0 1 multiplexed low address/data or data only 2 & 3 control i/o for uart, handshake channels, co unter/timers, general i/o and external interrupts 4 low address or general i/o port 0 port 0 can be assigned on a bit-by-bit basis as eit her general i/o or as address bits for external mem ory. the bits configured as i/o can be either all inputs or all outputs, they cannot be mixed. if configure d for outputs, they can be either push-pull or open-drain types. i/o direction is controlled by mode control register r241. push-pull or open-drain selection is controlled by mode control register r241. port 0 can be placed under handshake control handsh ake channel 1. any bits configured as i/o can be accessed via r208 . port 0 bits configured as address outputs cannot be accessed via the register, and initially the four lower bits are configured as addresses eight through twel ve. port 1 port 1 is bi-directional. port 1 is configured as e ither a byte wide mux'ed address(low byte)/data bus or as data bus only. this control is via the demux pin . the port address for port 1 is r209. port 1 drive characteristics can be selected to be either push/p ull or open drain. this control is via the mode/con trol register r241 bank0, controlregr241b0
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 62 of 80 1.888.824.4184 port 2 and 3 ports 2 and 3 provide external control inputs and o utputs for the uart, handshake channels and counter/timers. the pin assignments appear in figur e 60. bits not used for control i/o can be configur ed as general purpose i/o lines and/or external interr upt inputs. those bits configured for general i/o can be config ured individually for input for output. those configured for output can be individually configure d for (1) input or output and (2) open drain or pus h pull output. figure 60. pin assignments for port 2 and 3 port 2 bit function port 3 bit function 0 uart receive clock 0 uart receive clock 1 uart transmit 1 uart transmit 2 reserved 2 reserved 3 reserved 3 reserved 4 handshake 0 input 4 handshake 1 input/wait 5 handshake 0 output 5 handshake 1 output/dm 6 counter 0 input 6 counter 1 input 7 counter 0 i/o 7 counter 1 i/o port 4 port 4 can be assigned as general i/o or as the low er address byte in de-mux mode. as general i/o, eac h bit can be configured individually as input or outp ut, with either push-pull or open-drain outputs. i/ o directions is controlled by mode control reg r246. push-pull or open_drain selection is controlled by mode control reg r247. all port 4 inputs are schmit t-triggered. port 4 can be placed under handshake control handshake channel 0. port 4 register addres s is r212. uart the uart is a full-duplex asynchronous channel. it transmits and receives independently at 5 to 8 bits per character and contains options for even- or odd -bit parity and a wake-up feature. data can be read into or out of the uart via r239, bank 0. this single address is able to serve a full - duplex channel because it contains two complete 8-b it registers, one for the transmitter and the other for the receiver. the programming model for the uart i s outlined in r235 (uart transmit control), r236 (uart receive control), r237 (uart interrupt e nable), r238 (transmit interrupt register) r248/249 bank 1 (uart baud rate generator), r250/25 1 bank 1 (uart mode a/b registers).
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 63 of 80 1.888.824.4184 pins the uart uses the following port 2 and 3 pins: figure 61. port 2 and 3 pins port/pin uart function 2/0 receive clock 3/0 receive data 2/1 transmit clock 3/1 transmit data transmitter data is output on the uart when the uarts register is specified as the destination (dst) of an operation. this automatically adds the start bit, t he programmed parity bit and the programmed number of stop bits. it can also add a wake-up bit if that op tion is selected. the extra bits in r239 are ignored if the uart is p rogrammed to a 5-, 6-, or 7-bit character. depending on the programmed data rate, serial data is transmitted at a rate equal to 1, 1\16, 1\32 or 1\64 of the transmitter clock rate. all data is sent out on the falling edge of the clock input. when the uart has no data to send, it holds the out put marking (high). it can be programmed with the send break command to hold the output marking low ( spacing). this output marking continues until the command is cleared. receiver the uart begins receive operation when receive enab le (urc, bit 0) is set to high. after this, a low on the receive input pin for longer than half a bit time is interpreted as a start bit. the uart sampl es the data on the input pin in the middle of each clock c ycle until a complete byte is assembled. this compl eted byte is placed in the receive data register. if the 1x clock mode is selected, external bit sync hronization must be provided, and the input data is sampled on the rising edge of the clock. for character lengths of less than eight bits, the uart inserts 1s into the unused bits. and if parity is enabled, the parity bit is not stripped. the data b its, extra 1s and the parity bits are placed in the uart data register (uio). while the uart is assembling a byte in its input sh ift register, the cpu has time to service an interr upt and manipulate the data character in uio.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 64 of 80 1.888.824.4184 once the complete character is assembled, the uart checks it and performs the following actions: 1. sets the control character status bit, if it is an ascii control character. 2. checks the wake-up settings and completes any in dicated action. 3. checks to see if the calculated parity matches t he programmed parity bit, if parity is enabled. if they do not match, it sets the parity error bit in urc ( r236, bank 0), which remains set until reset by software. 4. resets the framing error bit (urc, bit 4), if th e character is assembled without any stop bits. thi s bit remains set until cleared by software. overrun errors occur when characters are received f aster than they are read. that is, when the uart ha s assembled a complete character before the cpu has r ead current character, the uart sets the overrun error bit (urc, bit 3), and the character currently in the receive buffer is lost. the overrun bit remains set until cleared by softwa re. address space the ia88c00 can access 64 kbytes of program memory and 64 kbytes of data memory. these spaces can be either combined or separate. if separate, they a re controlled by the dm line (port p35), which sele cts data memory when low and program memory when high. cpu program memory program memory occupies address 0 to 64k. external program memory is accessed by configuring ports 0 and/or 1 and/or 4 as the memory interface. the address/data lines are controlled by as, ds and r/w. the first 32 program memory bytes are reserved for interrupt vectors. the lowest address available for user programs is 32 (decimal). this value is automa tically loaded into the program counter after a hardware reset. port 0 can be configured to provide from 0 to 8 additional address lines. port 1 is us ed as an 8-bit multiplexed address/data port or as a data port when in de-mux mode. cpu data memory if separated from program memory by the dm optional output, the external cpu data memory space can be mapped anywhere from 0 to 64k (full 16-bit addre ss space). data memory uses the same address/data bit (port 1) and additional address (chosen from po rt 0) as program memory. the dm pin (p35) is mainly what distinguishes data memory from program memory. it is also distinguished by the fact that data memory can begin at address 0000h. figure 62 shows the system memory space.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 65 of 80 1.888.824.4184 65535 32 0 external program memory interrupt vectors program memory data memory external data memory 0 65535 figure 62. program and data memory address space
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 66 of 80 1.888.824.4184 absolute maximum ratings symbol description min max unit v do supply voltage* -0.3 +7.0 v t stg storage temp -65 +150 c t a oper ambient temp ? ? c * voltages on all pins with respect to gnd ? see ordering information caution stress that exceeds that presented above may cause permanent damage to the device. this is a stress rating only. acceptable operation of the device at any condition above that which is indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for an extended period may affect device reliability. standard test conditions the following characteristics apply to standard tes t conditions as noted. all voltages are referenced to v ss. positive current flows into the referenced pin (sta ndard test load). standard conditions are: 4.5v < v cc < 5.5v gnd C ov -40oc < t a < + 85oc from output under test +5v 1k 150 pf 400 ga figure 63. standard test load
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 67 of 80 1.888.824.4184 dc characteristics symbol parameter min max unit condition v ch clock input high voltage 3.5 v cc v driven by external clock generator v cl clock input low voltage -0.3 1.5 v driven by exter nal clock generator v ih input high voltage 2.2 v cc v v il input low voltage -0.3 0.8 v v rh reset input high voltage 3.8 v cc v v rl reset input low voltage -0.3 0.8 v v oh output high voltage 3.5 v i oh = -400 a v ol output low voltage 0.4 v i ol = +400 ma v il input leakage -10 10 a i ol output leakage -10 10 a i ir reset input current -50 a i cc v cc supply current 90 ma [1] i cc1 standby current 5 ma @ 20 mhz [2] 10 ma @ 30 mhz [2] i cc2 standby current 20 a [3] notes following are estimated values: 1. in this case all outputs and i/o pins are floati ng. 2. estimated values, not tested. halt mode is invok ed with uart ct0 and ct1 deactivated with all input pins tied to v cc or v ss . 3. estimated values, not tested. stop mode is invok ed with all input pins tied to v cc or v ss .
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 68 of 80 1.888.824.4184 ac electrical characteristics figure 64. external i/o or memory read and write t iming number symbol parameter 1 tda(as) address valid to /as rise delay 2 thas(a) /as rise to address valid 3 tdas(di) /as rise to data in required valid delay 4 twas /as low width 5 tdaz (dsr) address float to /ds (read) 6 twdsr /ds (read) low width 7 twdsw /ds (write) low width 8 tddsr (di) /ds (read) to data 9 thdsr (di) /ds rise (read) to data in hold time 10 tdds (a) /ds rise to address active delay 11 tdda (as) /ds rise to /as delay 12 tdr/w (as) r/w to as rise delay 13 tdds (r/w) ds rise to r/w valid delay 14 tddo (dsw) data out to /ds (write) delay 15 thdsw (do) /ds rise (write) to data out hold tim e 16 tda (di) address to data in required valid delay 17 tdas (dsr) /as rise to d/s (read) delay 18 tsdi (dsr) data in setup time to ds rise (read) 19 tddm (as) /dm to /as rise delay 20 tdds (dm) /ds rise to /dm valid delay 21 thds (a) /ds rise to address valid hold time 22 tww wait width (one wait) window 23 tdas (w) /as rise to wait delay
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 69 of 80 1.888.824.4184 figure 65. 20 mhz timing no. symbol normal min max extended min max 1 tda (as) 25 70 2 thas (a) 25 70 3 tdas (di) 180 375 4 twas 35 85 5 tdaz (dsr) 0 0 6 twdsr 140 285 7 twdsw 85 185 8 tddsr (di) 115 260 9 thdsr (di) 0 0 10 tdds (a) 25 25 11 tdds (as) 20 65 12 tdr/w (as) 25 70 13 tdds (r/w) 20 65 14 tddo (dsw) 30 70 15 thdsw (do) 20 65 16 tda (di) 205 445 17 tdas (dsr) 25 70 18 tsdi (dsr) 25 65 19 tddm (as) 20 65 20 tdds (dm) 20 65 21 thds (a) 20 65
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 70 of 80 1.888.824.4184 figure 66. 12 mhz timing no. symbol normal min max extended min max 1 tda (as) 55 135 2 thas (a) 55 135 3 tdas (di) 305 630 4 twas 70 150 5 tdaz (dsr) 0 0 6 twdsr 240 480 7 twdsw 150 320 8 tddsr (di) 215 440 9 thdsr (di) 0 0 10 tdds (a) 55 130 11 tdds (as) 45 125 12 tdr/w (as) 55 135 13 tdds (r/w) 45 125 14 tddo (dsw) 65 150 15 thdsw (do) 45 125 16 tda (di) 365 770 17 tdas (dsr) 55 135 18 tsdi (dsr) 25 25 19 tddm (as) 50 130 20 tdds (dm) 45 125 21 thds (a) 45 125
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 71 of 80 1.888.824.4184 figure 67. 25 mhz timing no. symbol normal min max extended min max 1 tda (as) 15 50 2 thas (a) 15 50 3 tdas (di) 140 280 4 twas 26 65 5 tdaz (dsr) 0 0 6 twdsr 110 220 7 twdsw 65 142 8 tddsr (di) 85 195 9 thdsr (di) 0 0 10 tdds (a) 20 55 11 tdds (as) 15 50 12 tdr/w (as) 15 50 13 tdds (r/w) 15 50 14 tddo (dsw) 20 50 15 thdsw (do) 15 50 16 tda (di) 155 330 17 tdas (dsr) 15 50 18 tsdi (dsr) 25 25 19 tddm (as) 10 45 20 tdds (dm) 15 50 21 thds (a) 15 50 input handshake timing 1 2 3 4 6 7 data in dav in rdy out 5 figure 68. fully interlocked mode (input handshake)
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 72 of 80 1.888.824.4184
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 73 of 80 1.888.824.4184 1 4 data in dav in 5 figure 69. strobed mode (input handshake) ac electrical characteristics input handshake no. symbol parameter min max notes* ? 1 tsdi(dav) data in to setup time 0 2 tddavlf(rdy) /dav fall input to rdy fall delay 2 00 1 3 thdi(rdy) data in hold time from rdy fall 0 4 twdav /dav in width 45 5 thd(dav) data in hold time from /dav fall 130 6 tddav(rdy) /dav rise input to rdy rise delay 100 2 7 tdrdyf(dav) rdy rise output to /dav rise delay 0 notes 1. standard test load 2. this time assumes user program reads data before /dav input goes high. rdy will not go high before data is read. * times are given in nanoseconds. ? times are preliminary and subject to change. output handshake timing 1 2 3 4 data out dav out rdy in 5 figure 70. fully interlocked mode (output handshake )
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 74 of 80 1.888.824.4184 1 data out dav out 6 figure 71. strobed mode (output handshake) ac electrical characteristics (12 mhz, 20 mhz) output handshake no. symbol parameter min max notes* ? 1 tddo(dav) data out to /dav fall delay 90 1, 2 2 tdrdyr(dav) rdy rise input to /dav fall delay 11 0 1 3 thdav(rdy) /dav fall output to rdy fall delay 0 4 tdrdy(dav) /rdy fall input to /dav rise delay 0 1 10 1 5 tddavor(rdy) /dav rise output to rdy rise delay 0 6 twdavo /dav output width 150 2 notes: 1. standard test load 2. time given is for zero value in deskew counter. for non-zero value of n where n = 1,2, 15 add 2 x n x tpc to the given time. ? times given are in nanoseconds. * times are preliminary and subject to change. erpom read timing 1 address out data in d 0 d y in a 0 a 13 figure 72. eprom read timing
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 75 of 80 1.888.824.4184 ac electrical characteristics (20 mhz) eprom read cycle no. symbol parameter min max notes ?* 1 tda(dr) address valid to read data required valid 170 1 notes 1. wait states add 167 ns to these times. ? all times are in nanoseconds and are for 12 m hz input frequency. * timings are preliminary and subject to change . wait timing sclk /as /ds /wait t1 t2 twait t3 a b c d tc tc e f g figure 73. wait timing description a skew of t1 sclk rise to /as fall 10.0 max b skew of t1 sclk rise to /as rise 10.0 max c skew of t2 sclk rise to read /ds fall 20.0 max d skew t2 sclk fall to write /ds fall 20.0 max e skew t3 sclk fall to /ds rise 20.0 max f /wait fall delay after t2 sclk fall to generate a t least 1 wait state 20.0 max g /wait fall delay after t2 sclk fall to prevent an additional wait state 15.0 max notes all figures are in nanoseconds.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 76 of 80 1.888.824.4184 de-multiplexed bus timing p0 demixed a/d bus p1 t1 t2 t3 clk p4 /as /ds r/w /dm a8 - a15 d0 - d7 a0 - a7 notes /as, /ds, r/w, /dm timing remains unchanged in demu xed a/d bus mode.
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 77 of 80 1.888.824.4184 package information .540 .560 24 25 48 1 2470 max d62r figure 74. 48-lead aerial view .015 .021 .100 typ .060 .090 .040 .060 .060 .075 .145 .165 .125 min .015 min figure 75. 48-lead side view 600 .620 009 .015 610 .650 figure 76. 48-lead end view
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 78 of 80 1.888.824.4184 .950 .958 .985 1.000 pin 1 i.d. 45 deg x .045 max .026 .030 050 +/-.001 typ aerial view figure 77. 68-lead package aerial view bottom view 27 43 26 10 9 44 60 61 68 1 figure 78. 68-lead package bottom view
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 79 of 80 1.888.824.4184 .045 x 45 deg side view .016 .020 .900 .980 dim. from center to center of radii .105 .115 .035r typ .020 .026 .170 .180 figure 79. 68-lead package side view
ia88c00 data sheet microcontroller as of production version -01 copyright ? 2005 eng21 1 0 30617-04 www.inno vasic innovasic.com innovasic semiconductor page 80 of 80 1.888.824.4184 ordering information innovasic semiconductor ? ?? ? part number package type temperature grades ia88c00-pdw48c (standard packaging) ia88c00-pdw48i (standard packaging) 48-pin plastic dual in- line package (dip) commercial industrial IA88C00-PDW48C-R (rohs packaging) ia88c00-pdw48i-r (rohs packaging) commercial industrial ia88c00-plc68c (standard packaging) ia88c00-plc68i (standard packaging) 68-pin plastic leaded chip carrier (plcc) commercial industrial ia88c00-plc68c-r (rohs packaging) ia88c00-plc68i-r (rohs packaging) commercial industrial

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